Cypress Semiconductor /psoc63 /SAR /CTRL

VREF buffer low power mode.

0 (PWR_100): full power (100 percent) (default), bypass cap, max clk_sar is 18MHz.

1 (PWR_80): 80 percent power

2 (PWR_60): 60 percent power

3 (PWR_50): 50 percent power

4 (PWR_40): 40 percent power

5 (PWR_30): 30 percent power

6 (PWR_20): 20 percent power

7 (PWR_10): 10 percent power

SARADC internal VREF selection.

0 (VREF0): VREF0 from PRB (VREF buffer on)

1 (VREF1): VREF1 from PRB (VREF buffer on)

2 (VREF2): VREF2 from PRB (VREF buffer on)

3 (VREF_AROUTE): VREF from AROUTE (VREF buffer on)

4 (VBGR): 1.024V from BandGap (VREF buffer on)

5 (VREF_EXT): External precision Vref direct from a pin (low impedance path).

6 (VDDA_DIV_2): Vdda/2 (VREF buffer on)

7 (VDDA): Vdda.

VREF bypass cap enable for when VREF buffer is on

SARADC internal NEG selection for Single ended conversion

0 (VSSA_KELVIN): NEG input of SARADC is connected to ‘vssa_kelvin’, gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high.

1 (ART_VSSA): NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC

2 (P1): NEG input of SARADC is connected to P1 pin of SARMUX

3 (P3): NEG input of SARADC is connected to P3 pin of SARMUX

4 (P5): NEG input of SARADC is connected to P5 pin of SARMUX

5 (P7): NEG input of SARADC is connected to P7 pin of SARMUX

6 (ACORE): NEG input of SARADC is connected to an ACORE in AROUTE

7 (VREF): NEG input of SARADC is shorted with VREF input of SARADC.

Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch.

Set the comparator latch delay in accordance with SAR conversion rate

0 (D2P5): 2.5ns delay, use this for 2.5Msps

1 (D4): 4.0ns delay, use this for 2.0Msps

2 (D10): 10ns delay, use this for 1.5Msps

3 (D12): 12ns delay, use this for 1.0Msps or less

Spare controls, not yet designated, for late changes done with an ECO

deprecated

For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. Setting this bit is critical to proper function of switches inside SARREF block.

Comparator power mode. (Sample rate TBD)

0 (P100): Power = 100 percent, use this for >2000Ksps

1 (P80): Power = 80 percent, use this for 1500-2000Ksps

2 (P60): Power = 60 percent, use this for 1000-1500Ksps

3 (P50): Power = 50 percent, use this for 500-1000Ksps

4 (P40): Power = 40 percent, use this for 250-500Ksps

5 (P30): Power = 30 percent, use this for 100-250Ksps

6 (P20): Power = 20 percent, use this for 100-250Ksps (TBD!)

7 (P10): Power = 10 percent, use this for <100Ksps

• 0: SARMUX IP disabled off during DeepSleep power mode
• 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1)

• 0: bypass clock domain synchronisation of the DSI config signals.
• 1: synchronize the DSI config signals to peripheral clock domain.

SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)

• 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations
• 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored

Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)

• 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations
• 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX

• 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgaiting) on write.
• 1: SAR IP enabled.